1. Technical Field
The present invention relates to a network switch providing communication between nodes that uses a BlockRAM (BRAM) memory of a Field Programmable Gate Array (FPGA) to store data.
2. Related Art
Traditional switching functions in network systems require the interconnection of various nodes, or modules that perform a specific function. Nodes can be formed on a single device, such as an Application Specific Integrated Circuit (ASIC), or multiple chips, with the nodes configured to communicate with one another. Communications are accomplished using direct communication links between the nodes over a circuit switched crossbar, or by using a bus structure.
The crossbar switch provides a set of connecting wires, with no support for the data formats that are transmitted between nodes or modules formed in the logic. The crossbar connection scheme while providing extremely low latency for traversal times between the nodes provides no support to the packets or cells or other types of data bursts that form the data interchange format between the nodes.
To support packet or cell data formats, cells or packets buffers can be provided at the input or output ports of the switch. The buffers then function to switch the packet or cell information packet or cell at a time. More sophisticated ASICs provide for switching of cell or packet data between nodes using busses, but they provide switching tailored for use in systems that use specific protocols such as Ethernet, Internet Protocol Version 4 and 6 (IPv4 and IPv6), PCI Express, Rapid I/O, Infiniband, etc. with support for cells/packets/data-grams or other types of data bursts associated with the respective protocols. A PCI express switch will not support other protocols or standards when it is supplied in an ASIC.
Programmable logic devices PLDs, such as Field Programmable Gate Arrays (FPGAs), allow for programming of multiple nodes within a single device with circuitry further programmed to provide for communication between the nodes. Communication between nodes is typically provided using a crossbar switch programmed using interconnect logic of the FPGA. Communication between nodes, however, can also be provided using a bus structure and data buffering using a memory. The memory device is typically used to store packets of data while the data is buffered and transferred between nodes. Programming the memory and scheduler for writing data to and reading data from the memory being transferred between nodes, however, uses a significant amount of logic available on the FPGA. Significantly more logic must be made available with a network data switch on an FPGA to accommodate a selection between all different types of data protocols a programmer might wish to use. Limited memory is available on the FPGA for storing data long term.
It would be desirable to provide a communication system for interconnecting nodes on an FPGA that can adapt to different communication protocols. It would further be desirable to provide such a communication systems that use minimal logic resources of the FPGA, leaving logic available for programming additional nodes.